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rev. 1.10 1 june 21, 2011 rev. 1.00 pb june 21, 2011 HT16C23/HT16C23g ram mapping 56*4 / 52*8 lcd driver controller features operating voltage: 2.4 ~ 5.5v internal 32khz rc oscillator bias: 1/3 or 1/4; duty:1/4 or 1/8 internal lcd bias generation with voltage- follower buffers i 2 c-bus interface two selectable lcd frame frequencies: 80hz or 160hz up to 52 x 8 bits ram for display data storage display patterns: C 56 x 4 patterns: 56 segments and 4 commons C 52 x 8 patterns: 52 segments and 8 commons versatile blinking modes r/w address auto increment internal 16-step voltage adjustment to adjust lcd operating voltage low power consumption provides v lcd pin to adjust lcd operating voltage manufactured in silicon gate cmos process package type: 48lqfp, 64lqfp, chip and goldbump chip. applications electronic meter water meter gas meter heat energy meter household appliance games telephone consumer electronics general description the HT16C23/HT16C23g device is a memory mapping and multi-function lcd controller driver. the display segments of the device are 224 patterns (56 segments and 4commons) or 416 patterns (52 segments and 8commons). the software confguration feature of the HT16C23/HT16C23g device makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16C23/ HT16C23g device communicates with most microprocessors / microcontrollers via a two-line bidirectional i 2 c-bus. block diagram lcd voltage selector column /segment driver output segment driver output display ram 52*8bits timing generator i2c controller com0 com3 seg4 vlcd vss sda scl internal rc oscillator power_on reset r op1 com4/seg0 com7/seg3 r op2 seg55 vdd lcd bias generator r 8 r op3 internal voltage adjustment op4 vcca2
rev. 1.10 2 june 21, 2011 HT16C23/HT16C23g pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 37 38 39 40 41 42 43 44 HT16C23 48 lqfp - a seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 vdd sda scl vss com0 com1 com2 com3 com4 com5 com6 com7 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 vlcd HT16C23 64 lqfp - a seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 vlcd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 37 38 39 40 41 42 43 44 HT16C23 48 lqfp - a seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 vdd sda scl vss com0 com1 com2 com3 com4 com5 com6 com7 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 HT16C23 64 lqfp - a seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 37 38 39 40 41 42 43 44 HT16C23 48 lqfp - a seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 vdd sda scl vss com0 com1 com2 com3 com4 com5 com6 com7 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 vlcd HT16C23 64 lqfp - a seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 vlcd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 37 38 39 40 41 42 43 44 HT16C23 48 lqfp - a seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 vdd sda scl vss com0 com1 com2 com3 com4 com5 com6 com7 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 HT16C23 64 lqfp - a seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 note: 1. application at v dd v v
rev. 1.10 3 june 21, 2011 HT16C23/HT16C23g pad assignment for cob (0, 0) 22 35 34 33 32 30 31 29 28 27 26 25 24 23 50 1 sda scl option vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 seg4 seg5 seg6 seg7 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 vlcd vcca2 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 vdd n.c. 68 67 66 65 64 63 62 61 58 59 57 56 55 54 53 52 51 60 36 49 48 47 46 45 44 43 42 41 40 39 38 37 2 3 4 6 5 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 chip size: 1843 x 2018m 2 note: 1. the option ( pad 5) must be bonded to v dd or foating. 2. the ic substrate should be connected to v ss in the pcb layout artwork. 3. vlcd (pad 68) and vcca2 (pad 1) must be bonded together for the application at v dd v lcd or v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 68) seg55 (pad 67) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 input null internal voltage adjustment is null vlcd support internal bias voltage 1 0 input output vlcd support internal bias voltage 1 1 input output vlcd support internal bias voltage 4. vdd (pad2) and vcca2 (pad 1) must be bonded together for the application at v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 68) seg55 (pad 67) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 output null detect the internal bias voltage vdd support internal bias voltage 1 0 floating output vdd support internal bias voltage 1 1 floating output vdd support internal bias voltage
rev. 1.10 4 june 21, 2011 HT16C23/HT16C23g pad coordinates for cob unit: m no name x y no name x y 1 vcca2 -788.05 905.4 35 seg23 780.15 -905.4 2 vdd -783.15 572.25 36 seg24 817.45 -582.35 3 sda -817.9 419.55 37 seg25 817.45 -497.35 4 scl -817.9 334.55 38 seg26 817.45 -412.35 5 option -817.9 249.55 39 seg27 817.45 -327.35 6 vss -817.9 164.55 40 seg28 817.45 -242.35 7 com0 -817.9 79.55 41 seg29 817.45 -157.35 8 com1 -817.9 -5.45 42 seg30 817.45 -72.35 9 n.c. -484.014 -35.6 43 seg31 817.45 12.65 10 com2 -817.9 -90.45 44 seg32 817.45 97.65 11 com3 -817.9 -175.45 45 seg33 817.45 182.65 12 com4/seg0 -817.9 -270.35 46 seg34 817.45 267.65 13 com5/seg1 -817.9 -355.35 47 seg35 817.45 352.65 14 com6/seg2 -817.9 -440.35 48 seg36 817.45 437.65 15 com7/seg3 -817.9 -525.35 49 seg37 817.45 522.65 16 seg4 -817.9 -613.1 50 seg38 817.45 607.65 17 seg5 -817.9 -698.1 51 seg39 741.95 905.4 18 seg6 -817.9 -783.1 52 seg40 656.95 905.4 19 seg7 -817.9 -868.1 53 seg41 571.95 905.4 20 seg8 -494.85 -905.4 54 seg42 486.95 905.4 21 seg9 -409.85 -905.4 55 seg43 401.95 905.4 22 seg10 -324.85 -905.4 56 seg44 316.95 905.4 23 seg11 -239.85 -905.4 57 seg45 231.95 905.4 24 seg12 -154.85 -905.4 58 seg46 146.95 905.4 25 seg13 -69.85 -905.4 59 seg47 61.95 905.4 26 seg14 15.15 -905.4 60 seg48 -23.05 905.4 27 seg15 100.15 -905.4 61 seg49 -108.05 905.4 28 seg16 185.15 -905.4 62 seg50 -193.05 905.4 29 seg17 270.15 -905.4 63 seg51 -278.05 905.4 30 seg18 355.15 -905.4 64 seg52 -363.05 905.4 31 seg19 440.15 -905.4 65 seg53 -448.05 905.4 32 seg20 525.15 -905.4 66 seg54 -533.05 905.4 33 seg21 610.15 -905.4 67 seg55 -618.05 905.4 34 seg22 695.15 -905.4 68 vlcd -703.05 905.4
rev. 1.10 5 june 21, 2011 HT16C23/HT16C23g pad assignment for goldbump chip (0, 0) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 73 72 71 70 69 68 67 66 65 64 83 82 81 80 79 78 77 76 75 74 93 1 94 92 91 90 89 88 87 86 85 84 63 62 51 60 61 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 note: vlcd (pad 21) must be connected to vcca2 (pad 22) in the pcb layout for the application at v dd v lcd or v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 21) seg55 (pad 14) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 input null internal voltage adjustment is null vlcd support internal bias voltage 1 0 input output vlcd support internal bias voltage 1 1 input output vlcd support internal bias voltage vdd (pad 19) must be connected to vcca2 (pad 22) in the pcb layout for the application at v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 21) seg55 (pad 14) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 output null detect the internal bias voltage vdd support internal bias voltage 1 0 floating output vdd support internal bias voltage 1 1 floating output vdd support internal bias voltage
rev. 1.10 6 june 21, 2011 HT16C23/HT16C23g pad dimensions for goldbump chip item number size unit x y chip size 2806 1080 m chip thickness 508 m pad pitch 1, 3~15, 38~50, 52~94 60 m 16~37 87 m bump size output pad 5~14, 39~48 60 40 m 54~93 40 60 m input pad 17~22 67 67 m dummy pad 3, 4, 15, 38, 49, 50 60 40 m 1, 52, 53, 94 40 60 m 16, 23~37 67 67 m bump height all pad 183 m alignment mark dimensions for goldbump chip item number size unit align_a 2 40um 20um 20um (-1330, 362.5) 10um 10um 10um 10um m align_b 51 20um 20um 20um 20um (1310, 362.5) 10um 10um 10um 10um m
rev. 1.10 7 june 21, 2011 HT16C23/HT16C23g pad coordinates for goldbump chip unit: m no name x y no name x y 1 dummy -1290 444.5 48 seg5 1308.5 151.25 3 dummy -1308.5 271.25 49 dummy 1308.5 211.25 4 dummy -1308.5 211.25 50 dummy 1308.5 271.25 5 seg46 -1308.5 151.25 52 dummy 1290 444.5 6 seg47 -1308.5 91.25 53 dummy 1230 444.5 7 seg48 -1308.5 31.25 54 seg6 1170 444.5 8 seg49 -1308.5 -28.75 55 seg7 1110 444.5 9 seg50 -1308.5 -88.75 56 seg8 1050 444.5 10 seg51 -1308.5 -148.75 57 seg9 990 444.5 11 seg52 -1308.5 -208.75 58 seg10 930 444.5 12 seg53 -1308.5 -268.75 59 seg11 870 444.5 13 seg54 -1308.5 -328.75 60 seg12 810 444.5 14 seg55 -1308.5 -388.75 61 seg13 750 444.5 15 dummy -1308.5 -448.75 62 seg14 690 444.5 16 dummy -1007.85 -436.872 63 seg15 630 444.5 17 sda -920.85 -436.872 64 seg16 570 444.5 18 scl -833.85 -436.872 65 seg17 510 444.5 19 vdd -746.85 -436.872 66 seg18 450 444.5 20 vss -594.45 -436.872 67 seg19 390 444.5 21 vlcd -507.45 -436.872 68 seg20 330 444.5 22 vcca2 -420.45 -436.872 69 seg21 270 444.5 23 dummy -234.45 -436.872 70 seg22 210 444.5 24 dummy -147.45 -436.872 71 seg23 150 444.5 25 dummy -60.45 -436.872 72 seg24 90 444.5 26 dummy 26.55 -436.872 73 seg25 30 444.5 27 dummy 113.55 -436.872 74 seg26 -30 444.5 28 dummy 200.55 -436.872 75 seg27 -90 444.5 29 dummy 287.55 -436.872 76 seg28 -150 444.5 30 dummy 374.55 -436.872 77 seg29 -210 444.5 31 dummy 461.55 -436.872 78 seg30 -270 444.5 32 dummy 548.55 -436.872 79 seg31 -330 444.5 33 dummy 635.55 -436.872 80 seg32 -390 444.5 34 dummy 722.55 -436.872 81 seg33 -450 444.5 35 dummy 809.55 -436.872 82 seg34 -510 444.5 36 dummy 896.55 -436.872 83 seg35 -570 444.5 37 dummy 983.55 -436.872 84 seg36 -630 444.5 38 dummy 1308.5 -448.75 85 seg37 -690 444.5 39 com0 1308.5 -388.75 86 seg38 -750 444.5 40 com1 1308.5 -328.75 87 seg39 -810 444.5 41 com2 1308.5 -268.75 88 seg40 -870 444.5 42 com3 1308.5 -208.75 89 seg41 -930 444.5 43 com4/seg0 1308.5 -148.75 90 seg42 -990 444.5 44 com5/seg1 1308.5 -88.75 91 seg43 -1050 444.5 45 com6/seg2 1308.5 -28.75 92 seg44 -1110 444.5 46 com7/seg3 1308.5 31.25 93 seg45 -1170 444.5 47 seg4 1308.5 91.25 94 dummy -1230 444.5
rev. 1.10 8 june 21, 2011 HT16C23/HT16C23g alignment mark coordinates for goldbump chip no name x y no name x y 2 align_a -1330 362.5 51 align_b 1310 362.5 pad description pad name type description sda i/o serial data input/output for i 2 c interface scl i serial clock input for i 2 c interface vdd positive power supply. vss negative power supply, ground. vlcd power supply for lcd driver. com0~com3 o lcd common outputs. com4/seg0 ~com7/seg3 o lcd common/segment multiplexed driver outputs seg4~seg55 o lcd segment outputs. vcca2 power supply for lcd bias generator. approximate internal connections vdd vss scl, sda (for schmit trigger type) vselect-on vselect-off com0~com7; seg0~seg55
rev. 1.10 9 june 21, 2011 HT16C23/HT16C23g absolute maximum ratings supply voltage ....................................................................................................................... v ss -0.3v to v ss +6.5v input voltage ......................................................................................................................... v ss -0.3v to v dd +0.3v storage temperature ........................................................................................................................ -55 c to 150c operating temperature ...................................................................................................................... -40 c to 85 c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics v ss = 0v; v dd =2.4 to 5.5v; ta = -40 to +85c. vcca2 pad is connected to vdd pad symbol parameter test condition min. typ. max. unit v dd condition v dd operating voltage 2.4 5.5 v v lcd operating voltage 2.4 5.5 v i dd operating current 3v no load, v lcd =v dd, 1/3bias, f lcd =80hz, lcd display on, internal system oscillator on, da0~da3 are set to 0000 25 40 a 5v 35 50 a i dd1 operating current 3v no load, v lcd =v dd, 1/3bias f lcd =80hz, lcd display off, internal system oscillator on, da0~da3 are set to 0000 2 5 a 5v 4 10 a i stb standby current 3v no load, v lcd =v dd , lcd display off, internal system oscillator off, 1 a 5v 2 a v ih input high voltage sda ,scl 0.7v dd v dd v v il input low voltage sda, scl 0 0.3v dd v i il input leakage current v in = v ss or v dd -1 1 a i ol low level output current 3v v ol =0.4v sda 3 ma 5v 6 ma i ol1 lcd com sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh1 lcd com source current 3v v lcd =3v, v oh =2.7v - 140 -230 a 5v v lcd =5v, v oh =4.5v - 300 -500 a i ol2 lcd seg sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh2 lcd seg source current 3v v lcd =3v, v oh =2.7v - 140 -230 a 5v v lcd =5v, v oh =4.5v - 300 -500 a
rev. 1.10 10 june 21, 2011 HT16C23/HT16C23g a.c. characteristics v ss = 0v; v dd = 2.4 to 5.5v; ta= -40 to +85c. vcca2 pad is connected to vdd pad symbol parameter test condition min. typ. max. unit v dd condition f lcd1 lcd frame frequency 4v 1/4 duty, ta =25 c 72 80 88 hz f lcd2 lcd frame frequency 4v 1/4 duty, ta =25 c 144 160 176 hz f lcd3 lcd frame frequency 4v 1/4 duty, ta=- 40 to +85c 52 80 124 h z f lcd4 lcd frame frequency 4v 1/4 duty, ta=- 40 to +85c 104 160 248 h z t off v dd off times v dd drop down to 0v 20 ms t sr v dd slew rate 0.05 v/ms note: if the conditions of power on reset timing are not satisfed during the power on/off sequence, the internal power on reset (por) circuit will not operate normally. if the v dd voltage drops below the minimum voltage of operating voltage spec. during operating, the power on reset timing conditions must also be satisfed. that is, the v dd voltage must drop to 0v and remain at 0v for 20ms (min.) before rising to the normal operating voltage. a.c. characteristics C i 2 c interface symbol parameter condition v dd =2.4v to 5.5v v dd =3.0v to 5.5v unit min. max. min. max. f scl clock frequency 100 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 1.3 s t hd: sta start condition hold time after this period, the frst clock pulse is generated 4 0.6 s t low scl low time 4.7 1.3 s t high scl high time 4 0.6 s t su: sta start condition setup time only relevant for repeated start condition. 4.7 0.6 s t hd: dat data hold time 0 0 ns t su: dat data setup time 250 100 ns t r sda and scl rise time note 1 0.3 s t f sda and scl fall time note 0.3 0.3 s t su: sto stop condition set-up time 4 0.6 s t aa output valid from clock 3.5 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns note: these parameters are periodically sampled but not 100% tested.
rev. 1.10 11 june 21, 2011 HT16C23/HT16C23g timing diagrams i 2 c timing sda scl t f t hd:sta t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out power on reset timing
rev. 1.10 12 june 21, 2011 HT16C23/HT16C23g functional description power-on reset when the power is applied, the device is initialized by an internal power-on reset circuit. the status of the internal circuits after initialization is as follows: all common / segment outputs are set to v dd when vcca2 pad is connected to vdd pad. all common / segment outputs are set to v lcd when vcca2 pad is connected to vlcd pad. the drive mode 1/4 duty output and 1/3 bias is selected for 64 pin lqfp package. the drive mode 1/8 duty output and 1/3 bias is selected for 48 pin lqfp package. the system oscillator and the lcd bias generator are off state. lcd display is off state. internal voltage adjustment function is enabled. the segment / vlcd shared pin is set as the segment pin. detection switch for the vlcd pin is disabled. frame frequency is set to 80hz. blinking function is switched off data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset action. display memory C ram structure the display ram is static 52 x 8-bits ram which stores the lcd data. logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, logic 0 indicates the off state. the contents of the ram data are directly mapped to the lcd data. the first ram column corresponds to the segments operated with respect to com0. in multiplexed lcd applications the segment data of the second, third and fourth column of the display ram are time-multiplexed with com1, com2 and com3 respectively. the following is a mapping from the ram data to the lcd pattern: output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg7 seg6 03h seg9 seg8 04h seg11 seg10 05h seg55 seg54 1bh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 56x4 display mode
rev. 1.10 13 june 21, 2011 HT16C23/HT16C23g output com7/ seg3 com6/ seg2 com5/ seg1 com4/ seg0 com3 com2 com1 com0 address seg4 00h seg5 01h seg6 02h seg7 03h seg8 04h seg9 05h seg55 33h d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 52x8 display mode d 7 d 6 d 5 d 4 d3 d2 d1 d0 msb lsb system oscillator the timing for the internal logic and the lcd drive signals are generated by an internal oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. during initial system power on the system oscillator will be in the stop state. lcd b ias g enerator the full-scale lcd voltage (v op ) is obtained from (v lcd C v ss ). the lcd voltage may be temperature compensated externally through the voltage supply to the v lcd pin. fractional lcd biasing voltages, known as 1/3 or 1/4 bias voltage, are obtained from an internal voltage divider of four series resistors connected between v lcd and v ss . the centre resistor can be switched out of circuits to provide a 1/3bias voltage level confguration.
rev. 1.10 14 june 21, 2011 HT16C23/HT16C23g lcd d rive m ode w aveforms when the lcd drive mode is selected as 1/4 duty and 1/3 bias, the waveform and lcd display is shown as follows: seg n+2 seg n+2 seg n seg n com0 com0 com1 com1 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd com2 com2 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 waveforms for 1/4 duty drive mode with1/3 bias (v op =v lcd -v ss ) note: t lcd =1/f lcd
rev. 1.10 15 june 21, 2011 HT16C23/HT16C23g when the lcd drive mode is selected as 1/8 duty and 1/4bias, the waveform and lcd display is shown as follows: com0 com0 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com1 com1 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com2 com2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop /4 v lcd - 3vop/4 com3 com3 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com4 com4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com5 com5 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com6 com6 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com7 com7 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop /4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n seg n v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+1 seg n+1 v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+2 seg n+2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+3 seg n+3 v lcd v lcd waveforms for 1/8 duty drive mode with1/4 bias (v op =v lcd -v ss ) note: t lcd =1/f lcd
rev. 1.10 16 june 21, 2011 HT16C23/HT16C23g segment driver o utputs the lcd drive section includes 56 segment outputs seg0~seg55 or 52 segment outputs seg4~seg55 which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. the unused segment outputs should be left open-circuit when less than 56 or 52 segment outputs are required. c olumn driver o utputs the lcd drive section includes 4 column outputs com0~com3 or 8 column outputs com0~com7 which should be connected directly to the lcd panel. the column output signals are generated in accordance with the selected lcd drive mode. the unused column outputs should be left open-circuit if less than 4 or 8 column outputs are required. address p ointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the address pointer by the address pointer command. blinker function the device contains versatile blinking capabilities. the whole display can be blinked at frequencies selected by the blink command. the blinking frequency is a subdivided ratio of the system frequency. the ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: blinking mode operating mode ratio blinking frequency (hz) 0 0 blink off 1 f sys / 16384hz 2 2 f sys / 32768hz 1 3 f sys / 65536hz 0.5 frame frequency the HT16C23/HT16C23g device provides two frame frequencies selected with mode set command known as 80hz and 160hz respectively.
rev. 1.10 17 june 21, 2011 HT16C23/HT16C23g internal vlcd voltage adjustment the internal v lcd adjustment contains four resistors in series and a 4-bit programmable analog switch which can provide sixteen voltage adjustment options using the v lcd voltage adjustment command. the internal v lcd adjustment structure is shown in the diagram: r internal voltage adjustment lcd bias generator v lcd pad r r r ve bit de bit v cca2 pad v dd pad the relationship between the programmable 4-bit analog switch and the v lcd output voltage is shown in the table: 1. when vcca2 pad is connected to vdd pad bias da3~da0 1/3 1/4 note 00h 1.000*v dd 1.000*v dd default value 01h 0. 944 *v dd 0.957*v dd 02h 0. 894 *v dd 0.918*v dd 03h 0.8 49 *v dd 0.882*v dd 04h 0.8 08 *v dd 0.849*v dd 05h 0. 771 *v dd 0.818*v dd 06h 0.7 38 *v dd 0.789*v dd 07h 0.7 07 *v dd 0.763*v dd 08h 0. 678 *v dd 0.738*v dd 09h 0. 652 *v dd 0.714*v dd 0ah 0.6 28 *v dd 0.692*v dd 0bh 0.6 05 *v dd 0.672*v dd 0ch 0. 584 *v dd 0.652*v dd 0dh 0. 565 *v dd 0.634*v dd 0eh 0. 547 *v dd 0.616*v dd 0fh 0. 529 *v dd 0.600*v dd
rev. 1.10 18 june 21, 2011 HT16C23/HT16C23g 2. when vcca2 pad is connected to vlcd pad bias da3~da0 1/3 1/4 note 00h 1.000*v lcd 1.000* v lcd default value 01h 0.944* v lcd 0.957* v lcd 02h 0.894* v lcd 0.918* v lcd 03h 0.849* v lcd 0.882* v lcd 04h 0.808* v lcd 0.849* v lcd 05h 0.771* v lcd 0.818* v lcd 06h 0.738* v lcd 0.789* v lcd 07h 0.707* v lcd 0.763* v lcd 08h 0.678* v lcd 0.738* v lcd 09h 0.652* v lcd 0.714* v lcd 0ah 0.628* v lcd 0.692* v lcd 0bh 0.605* v lcd 0.672*v dd 0ch 0.584* v lcd 0.652* v lcd 0dh 0.565* v lcd 0.634* v lcd 0eh 0.547* v lcd 0.616* v lcd 0fh 0.529* v lcd 0.600* v lcd i 2 c serial interface the device supports i 2 c serial interface. the i 2 c bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line, sda, and a serial clock line, scl. both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7k. when the bus is free, both lines are high. devices connected to the bus must have open-drain or open-collector outputs to implement a wired- or function. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the serial clock. the high or low state of the data line can only change when the clock signal on the scl line is low as shown in the diagram. sda scl data line stable, data valid chang of data allowed start and stop conditions a high to low transition on the sda line while scl is high defnes a start condition. a low to high transition on the sda line while scl is high defnes a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in some respects, the start(s) and repeated start (sr) conditions are functionally identical.
rev. 1.10 19 june 21, 2011 HT16C23/HT16C23g p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bit long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signifcant bit, msb, frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3-8 9 ack p sr acknowledge each bytes of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level placed on the bus by the receiver. the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge, ack, after the reception of each byte. the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. a master receiver must signal an end of data to the slave by generating a not-acknowledge, nack, bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9 th pulse to not acknowledge. the master will generate a stop or repeated start condition. s 1 2 7 8 9 clock pulse for acknowledgement data output by transmitter data outptu by receiver scl from master acknowledge not acknowledge start condition
rev. 1.10 20 june 21, 2011 HT16C23/HT16C23g s lave addressing the slave address byte is the frst byte received following the st art condition form the master device. the frst seven bits of the frst byte make up the slave address. the eighth bit defnes a read or write operation to be performed. when the r/ w bit is 1, then a read operation is selected. a 0 selects a write operation. the HT16C23/HT16C23g address bits are 0111110. when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. slave address 0 1 1 1 1 1 0 r/w msb lsb write operation byte writes operation command byte a command byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a command setting byte and a stop condition for a command byte write operation. slave address ack write command byte ack s 0 1 1 1 1 1 0 0 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 command setting ack p 2 nd bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 command byte write operation display ram single data byte a display ram data byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a valid register address byte, a data byte and a stop condition. slave address ack write command byte ack s 0 1 1 1 1 1 0 0 data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 register address byte ack 2 nd 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 display ram single data byte write operation
rev. 1.10 21 june 21, 2011 HT16C23/HT16C23g display ram page write operation after a start condition the slave address with the r/ w bit is placed on the bus followed with a command byte and the specifed display ram register address of which the contents are written to the internal address pointer. the data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse. after the internal address point reaches the maximum memory address, which is 1bh for 1/4 duty drive mode or 33h for 1/8 duty drive mode, the address pointer will be reset to 00h. slave address ack write ack s 0 1 1 1 1 1 0 0 ack 2 nd ack data byte p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack data byte d7 d6 d5 d4 d3 d2 d1 d0 1 st data ack register address byte command byte 1 st bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 n bytes display ram data write operation d isplay ram read operation in this mode, the master reads the HT16C23/HT16C23g data after setting the slave address. following the r/ w bit (=0) is an acknowledge bit, a command byte and the register address byte which is written to the internal address pointer. after the start address of the read operation has been confgured, another start condition and the slave address transferred on the bus followed by the r/ w bit (=1). then the msb of the data which was addressed is transmitted frst on the i 2 c bus. the address pointer is only incremented by 1 after the reception of an acknowledge clock. that means that if the device is confgured to transmit the data at the address of a n+1 , the master will read and acknowledge the transferred new data byte and the address pointer is incremented to a n+2 . after the internal address pointer reaches the maximum memory address, which is 1bh for 1/4 duty drive mode or 33h for 1/8 duty drive mode, the address pointer will be reset to 00h. this cycle of reading consecutive addresses will continue until the master sends a stop condition. ack write ack p slave address s 0 1 1 1 1 1 0 0 data byte nack d7 d6 d5 d4 d3 d2 d1 d0 1 st data data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack ack device address read s 0 1 1 1 1 1 0 1 ack register address byte command byte 1 st 2 nd bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
rev. 1.10 22 june 21, 2011 HT16C23/HT16C23g command summary display data input command this command sends data from mcu to memory map of the HT16C23/HT16C23g device. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def display data input/output command 1 st 1 0 0 0 0 0 0 0 w address pointer 2 nd x x a5 a4 a3 a2 a1 a0 display data start address of memory map w 00h note: power on status: the address is set to 00h. if the programmed command is not defned, the function will not be af fected. for 1/4 duty drive mode after reaching the memory location 1bh, the pointer will reset to 00h. for 1/8 duty drive mode after reaching the memory location 33h, the pointer will reset to 00h. d rive m ode command function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def driver mode setting command 1 st 1 0 0 0 0 0 1 0 w duty and bias setting 2 nd x x x x x x duty bias no matter what duty bit is set, 1/8 duty drive mode is only available for 48 lqfp. w 00h note: bit duty bias duty bias 0 0 1/4duty 1/3bias 0 1 1/4duty 1/4bias 1 0 1/8duty 1/3bias 1 1 1/8duty 1/4bias power on status: the drive mode 1/4 duty output and 1/3 bias is selected. if the programmed command is not defned, the function will not be af fected.
rev. 1.10 23 june 21, 2011 HT16C23/HT16C23g system mode c ommand this command controls the internal system oscillator on/off and display on/off. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def system mode setting command 1 st 1 0 0 0 0 1 0 0 w system oscillator and display on/off setting 2 nd x x x x x x s e w 00h note: bit internal system oscillator lcd display s e 0 x off off 1 0 on off 1 1 on on power on status: display off and disable the internal system oscillator. if the programmed command is not defned, the function will not be af fected. f rame frequency command this command selects the frame frequency. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def frame frequency command 1 st 1 0 0 0 0 1 1 0 w frame frequency setting 2 nd x x x x x x x f w 00h note: bit frame frequency f 0 80hz 1 160hz power on status: frame frequency is set to 80hz. if the programmed command is not defned, the function will not be af fected.
rev. 1.10 24 june 21, 2011 HT16C23/HT16C23g blinking frequency command this command defnes the blinking frequency of the display modes. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def blinking frequency command 1 st 1 0 0 0 1 0 0 0 w blinking frequency setting 2 nd x x x x x x bk1 bk0 w 00h note: bit blinking frequency bk1 bk0 0 0 blinking off 0 1 2hz 1 0 1hz 1 1 0.5hz power on status: blinking function is switched off. if the programmed command is not defned, the function will not be af fected.
rev. 1.10 25 june 21, 2011 HT16C23/HT16C23g internal voltage adjustment (iva) setting command the internal voltage (v lcd ) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting the lcd operating voltage adjustment command. function byte bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note r/w def iva command 1 st 1 0 0 0 1 0 1 0 w iva control 2 nd x x de ve da3 da2 da1 da0 the segment/vlcd shared pin can be programmed via the de bit. the ve bit is used to enable or disable the internal voltage adjustment is supply voltage to bias voltage. the da3~da0 bits can be used to adjust the v lcd output voltage. w 30h note: bit segment 55/ vlcd shared pin select internal voltage adjustment note de ve 0 0 vlcd off the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vlcd. the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vdd. if the vlcd pin is connected to the vdd pin, the internal voltage follower (op4) must be disabled by setting the da3~da0 bits as 0000. 0 1 vlcd on when vcca2 is connected to vlcd, internal voltage adjustment can not be used to adjust internal bias voltage. (bias voltage is supplied by the external vlcd pin) when vcca2 is connected to vdd, internal voltage adjustment can not be used to adjust internal bias voltage when vlcd pin is supplies with external voltage.(recommend: can not be used) when vcca2 is connected to vdd, internal voltage adjustment can be used to adjust internal bias voltage when vlcd pin is foating and internal voltage adjustment is enable.(bias voltage is supplied by the internal voltage adjustment) 1 0 segment 55 off the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vlcd. the bias voltage is supplied by the external vdd power when vcca2 is connected to vdd. the internal voltage-follower (op4) is disabled automatically and da3~da0 dont care. 1 1 segment 55 on when vcca2 is connected to vlcd, internal voltage adjustment can be used to adjust internal bias voltage when vlcd pin is supplies with external voltage and internal voltage adjustment is enable. (bias voltage is supplied by the internal voltage adjustment) when vcca2 is connected to vdd, internal voltage adjustment can be used to adjust internal bias voltage when internal voltage adjustment is enable.(bias voltage is supplied by the internal voltage adjustment) power on status: enable the internal voltage adjustment and the segment/vlcd pin is set as the segment pin. when the da0~da3 bits are set to 0000, the internal voltage-follower (op4) is disabled. when the da0~da3 bits are set to other values except 0000, the internal voltage follower (op4) is enabled. if the programmed command is not defned, the function will not be af fected.
rev. 1.10 26 june 21, 2011 HT16C23/HT16C23g operation fow chart access procedures are illustrated below by means of the fowcharts. initialization power on segment / vlcd shared pin setting internal lcd frame frequency setting internal lcd bias and duty setting lcd blinking frequency setting next processing
rev. 1.10 27 june 21, 2011 HT16C23/HT16C23g display data re ad/ write (address setting) start next processing display ram data write address setting display on and enable internal system clock
rev. 1.10 28 june 21, 2011 HT16C23/HT16C23g s egment / vlcd shared pin and internal voltage adjustment setting segment / vlcd share pin setting the bias voltage is supplied by programmable internal voltage adjustment one external resistor must be connected between to vlcd pin and vdd pin to determine the bias voltage internal voltage adjustment enable ? the external mcu can detect the voltage of vlcd pin yes no start set as segment pin the bias voltage is supplied by internal vdd power next processing set as vlcd pin internal voltage adjustment enable ? no yes
rev. 1.10 29 june 21, 2011 HT16C23/HT16C23g application circuits 64 pin package 1/4 duty lcd panel com0~com3 seg0~seg54 com0~com3 seg0~seg54 scl sda vdd vss host vdd vss HT16C23 vdd vss 0.1uf vlcd 4.7k 4.7k 0.1uf vlcd 1/8 duty lcd panel com0~com7 seg0~seg50 com0~com7 seg4~seg54 scl sda vdd vss host vdd vss HT16C23 vdd vss 0.1uf vlcd 4.7k 4.7k 0.1uf vlcd
rev. 1.10 30 june 21, 2011 HT16C23/HT16C23g 48 pin package (the 48 pin package supports lcd 1/8 duty only) lcd panel com0~com7 seg0~seg34 com0~com7 seg4~seg38 scl sda vdd vss host vdd vss HT16C23 vdd vss 0.1uf vlcd 4.7k 4.7k 0.1uf vlcd
rev. 1.10 31 june 21, 2011 HT16C23/HT16C23g package information 48-pin lqfp (7mmx7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.020 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.20 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7
rev. 1.10 32 june 21, 2011 HT16C23/HT16C23g 64-pin lqfp (7mmx7mm) outline dimensions lqfp outline dimensions 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.016 f 0.005 0.009 g 0.053 0.057 h 0.063 i 0.002 0.006 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 07 package information 1 february 8, 2010 symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.002 D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.23 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.20 0 D 7
rev. 1.10 33 june 21, 2011 HT16C23/HT16C23g holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .
rev. 1.10 34 june 21, 2011 HT16C23/HT16C23g
rev. 1.10 35 june 21, 2011 HT16C23/HT16C23g

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